Laser-based semiconductor processing systems are generally used, for example, to drill, machine, trim, sever, scribe, mark, cleave, make, heat, alter, diffuse, anneal, and/or measure a structure or its material on or within a semiconductor substrate. To improve throughput during fabrication of integrated circuits (ICs), it is also generally desirable that laser-based processing systems accurately and quickly process selected structures on or within the semiconductor substrate. However, conventional laser-based processing systems are typically tuned and operated with a conservative set of parameters to provide good accuracy for all types of ICs intended to be processed by the system. This “one-size-fits-all” approach often results in reduced processing speeds and overall reduced throughput.
A semiconductor link processing system, for example, typically provides the same level of accuracy when severing links on any IC. During fabrication, ICs often incur defects for various reasons. For that reason, IC devices are usually designed to include redundant circuit elements, such as spare rows and columns of memory cells in semiconductor memory devices, e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM), or an embedded memory. Such devices are also designed to include particular laser-severable links between electrical contacts of the redundant circuit elements. Such links can be removed, for example, to disconnect a defective memory cell and to substitute a replacement redundant cell. Links may also be removed for identification, configuration and voltage adjustment. Similar techniques are also used to sever links in order to program or configure logic products, such as gate arrays or application-specific integrated circuits (ASICs). After an IC has been fabricated, its circuit elements are tested for defects, and the locations of defects may be recorded in a database. Combined with positional information regarding the layout of the IC and the location of its circuit elements, a laser-based link processing system can be employed to remove selected links so as to make the IC useful.
Laser-severable links are typically about 0.5 to 1 microns (μm) thick, about 0.5 to 1 μm wide, and about 8 μm in length. Circuit elements in an IC, and thus links between those elements, are typically arranged in a regular geometric arrangement, such as in regular rows. In a typical row of links, the center-to-center pitch between adjacent links is about 2 to 3 μm. These dimensions are representative, and are declining as technological advances allow for the fabrication of workpieces with smaller features and the creation of laser processing systems with greater accuracy and smaller focused laser beam spots. Although the most prevalent link materials have been polysilicon and like compositions, memory manufacturers have more recently adopted a variety of more electrically conductive metallic link materials that may include, but are not limited to, aluminum, copper, gold nickel, titanium, tungsten, platinum, as well as other metals, metal alloys, metal nitrides such as titanium or tantalum nitride, metal silicides such as tungsten silicide, or other metal-like materials.
Conventional laser-based semiconductor link processing systems focus a single pulse of laser output having a pulse width of about 4 to 30 nanoseconds (ns) at each link. The laser beam is incident upon the IC with a footprint or spot size large enough to remove one and only one link at a time. When a laser pulse impinges a polysilicon or metal link positioned above a silicon substrate and between component layers of a passivation layer stack including an overlying passivation layer, which is typically 2000-10,000 angstroms (Å) thick, and an underlying passivation layer, the silicon substrate absorbs a relatively small proportional quantity of infrared (IR) radiation and the passivation layers (silicon dioxide or silicon nitride) are relatively transparent to IR radiation. IR and visible laser wavelengths (e.g., 0.532 μm, 1.047 μm, 1.064 μm, 1.321 μm, and 1.34 μm) have been employed for more than 20 years to remove circuit links.
Many conventional semiconductor link processing systems employ a single laser pulse focused into a small spot for link removal. Banks of links to be removed are typically arranged on the wafer in a straight row, an illustrative one of which is shown in FIG. 20. The row need not be perfectly straight, although typically it is quite straight. The links are processed by the system in a link run 120, which is also referred to as an on-the-fly (“OTF”) run. During a link run, the laser beam is pulsed as a stage positioner passes the row of links across the location of a focused laser spot 110. The stage typically moves along a single axis at a time and does not stop at each link position. Thus, the link run is a processing pass down a row of links in a generally lengthwise direction (e.g., horizontally across the page as shown). Moreover, the lengthwise direction of link run 120 need not be exactly perpendicular to the lengthwise direction of the individual links that constitute the row, although that is typically true.
Impinging on selected links in link run 120 is a laser beam whose propagation path is along an axis. The position at which that axis intersects the workpiece continually advances along link run 120 while pulsing the laser to selectively remove links. The laser is triggered to emit a pulse and sever a link when the wafer and optical components have a relative position such that the pulse energy impinges upon the link (e.g., trigger position 130). Some of the links are not irradiated and left as unprocessed links 140, while others are irradiated to become severed links 150.
FIG. 21 illustrates a typical link processing system that adjusts the position of the spot 110 by moving a wafer 240 in an X-Y plane underneath a stationary optics table 210. Optics table 210 supports a laser 220, a mirror 225, a focusing lens 230, and possibly other optical hardware. Wafer 240 is moved underneath in the X-Y plane by placing it on a chuck 250 that is carried by a motion stage 260.
FIG. 22 depicts the processing of wafer 240. A conventional sequential link blowing process requires scanning X-Y motion stage 260 across wafer 240 once for each link run. Repeatedly scanning back and forth across wafer 240 results in complete wafer processing. A machine typically scans back and forth processing all X-axis link runs 310 (shown with solid lines) before processing Y-axis link runs 320 (shown in dashed lines). This example is merely illustrative. Other configurations of link runs and processing modalities are possible. For example, it is possible to process links by moving the wafer or optics rail. In addition, link banks and link runs may not be processed with continuous motion.
For a wafer 240 comprising DRAM, for example, memory cells (not shown) may be located in areas 322 between X-axis link runs 310 and Y-axis link runs 320. For illustrative purposes, a portion of wafer 240 near an intersection of an X-axis link run 310 and a Y-axis link run 320 is magnified to illustrate a plurality of links 324 arranged in groups or link banks. Generally, the link banks are near the center of a die, near decoder circuitry, and not above any of the array of memory cells. Links 324 cover a relatively small area of the total wafer 240.
System parameters that may impact the time spent executing link runs, and thus throughput, include the laser pulse repetition frequency (PRF) and motion stage parameters such as stage acceleration, bandwidth, settling time, and the commanded stage trajectory. The commanded stage trajectory includes acceleration and deceleration segments, constant velocity processing of link banks, and “gap profiling” or accelerating over large gaps between links to be processed in a link run.
These and other system parameters may change between semiconductor wafers, between different types of semiconductor wafers, and/or with time. However, conventional semiconductor link processing systems typically use predetermined hardware configurations and motion profiling parameters, regardless of the differences between semiconductor wafers and/or system characteristics that change with time. Thus, processing accuracy may exceed expected or desired levels at the cost of reduced throughput for some semiconductor wafers.